<HTML><HEAD><TITLE>Device Usage Statistics Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'><H3>Device Usage Page (usage_statistics_webtalk.html)</H3>This HTML page displays the device usage statistics that will be sent to Xilinx.<BR>To see the actual file transmitted to Xilinx, please click <A HREF="./usage_statistics_webtalk.xml">here</A>.<BR><BR><HR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>software_version_and_target_device</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>beta</B></TD><TD>FALSE</TD>
  <TD BGCOLOR='#DBE5F1'><B>build_version</B></TD><TD>2405991</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>date_generated</B></TD><TD>Mon Nov 16 08:41:33 2020</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_platform</B></TD><TD>WIN64</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>product_version</B></TD><TD>Vivado v2018.3 (64-bit)</TD>
  <TD BGCOLOR='#DBE5F1'><B>project_id</B></TD><TD>dbb1d1cd66db4fc8a3e298947fa72d12</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>project_iteration</B></TD><TD>12</TD>
  <TD BGCOLOR='#DBE5F1'><B>random_id</B></TD><TD>db2ee620afd557248d3c895171b907e2</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>registration_id</B></TD><TD>db2ee620afd557248d3c895171b907e2</TD>
  <TD BGCOLOR='#DBE5F1'><B>route_design</B></TD><TD>TRUE</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_device</B></TD><TD>xc7a35t</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_family</B></TD><TD>artix7</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>target_package</B></TD><TD>csg324</TD>
  <TD BGCOLOR='#DBE5F1'><B>target_speed</B></TD><TD>-1</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>tool_flow</B></TD><TD>Vivado</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>user_environment</B></TD></TR>
<TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>cpu_name</B></TD><TD>Intel(R) Core(TM) i7-8700 CPU @ 3.20GHz</TD>
  <TD BGCOLOR='#DBE5F1'><B>cpu_speed</B></TD><TD>3192 MHz</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>os_name</B></TD><TD>Microsoft Windows 8 or later , 64-bit</TD>
  <TD BGCOLOR='#DBE5F1'><B>os_release</B></TD><TD>major release  (build 9200)</TD>
</TR><TR ALIGN='LEFT'>  <TD BGCOLOR='#DBE5F1'><B>system_ram</B></TD><TD>17.000 GB</TD>
  <TD BGCOLOR='#DBE5F1'><B>total_processors</B></TD><TD>1</TD>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='4'><B>vivado_usage</B></TD></TR>
<TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>gui_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>abstractcombinedpanel_remove_selected_elements=1</TD>
   <TD>addsrcwizard_specify_hdl_netlist_block_design=1</TD>
   <TD>addsrcwizard_specify_or_create_constraint_files=1</TD>
   <TD>basedialog_cancel=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>basedialog_ok=119</TD>
   <TD>basedialog_yes=13</TD>
   <TD>checktimingsectionpanel_check_timing_selection_table=20</TD>
   <TD>cmdmsgdialog_messages=9</TD>
</TR><TR ALIGN='LEFT'>   <TD>cmdmsgdialog_ok=5</TD>
   <TD>cmdmsgdialog_open_messages_view=1</TD>
   <TD>constraintschooserpanel_add_existing_or_create_new_constraints=2</TD>
   <TD>constraintschooserpanel_add_files=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>constraintschooserpanel_create_file=1</TD>
   <TD>createconstraintsfilepanel_file_name=1</TD>
   <TD>createsrcfiledialog_file_name=10</TD>
   <TD>definemodulesdialog_define_modules_and_specify_io_ports=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>editcreategeneratedclocktablepanel_edit_create_generated_clock_table=1</TD>
   <TD>filesetpanel_file_set_panel_tree=475</TD>
   <TD>flownavigatortreepanel_flow_navigator_tree=65</TD>
   <TD>fpgachooser_fpga_table=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>gettingstartedview_create_new_project=1</TD>
   <TD>graphicalview_zoom_in=7</TD>
   <TD>graphicalview_zoom_out=35</TD>
   <TD>hardwaretreepanel_hardware_tree_table=22</TD>
</TR><TR ALIGN='LEFT'>   <TD>hardwareview_expand_next_level=1</TD>
   <TD>launchpanel_generate_scripts_only=1</TD>
   <TD>mainmenumgr_checkpoint=4</TD>
   <TD>mainmenumgr_constraints=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_edit=6</TD>
   <TD>mainmenumgr_export=5</TD>
   <TD>mainmenumgr_file=6</TD>
   <TD>mainmenumgr_flow=8</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_help=4</TD>
   <TD>mainmenumgr_import=2</TD>
   <TD>mainmenumgr_ip=5</TD>
   <TD>mainmenumgr_project=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_reports=9</TD>
   <TD>mainmenumgr_text_editor=6</TD>
   <TD>mainmenumgr_tools=8</TD>
   <TD>mainmenumgr_view=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>mainmenumgr_window=14</TD>
   <TD>maintoolbarmgr_run=12</TD>
   <TD>mainwinmenumgr_layout=14</TD>
   <TD>msgtreepanel_message_view_tree=53</TD>
</TR><TR ALIGN='LEFT'>   <TD>msgview_error_messages=1</TD>
   <TD>msgview_information_messages=1</TD>
   <TD>msgview_warning_messages=3</TD>
   <TD>navigabletimingreporttab_timing_report_navigation_tree=13</TD>
</TR><TR ALIGN='LEFT'>   <TD>netlistschematicview_show_io_ports_in_this_schematic=1</TD>
   <TD>netlistschmenuandmouse_report_timing=3</TD>
   <TD>netlistschmenuandmouse_view=1</TD>
   <TD>netlisttreeview_netlist_tree=6</TD>
</TR><TR ALIGN='LEFT'>   <TD>newprojectwizard_do_not_specify_sources_at_this_time=1</TD>
   <TD>pacommandnames_add_sources=10</TD>
   <TD>pacommandnames_auto_connect_target=9</TD>
   <TD>pacommandnames_auto_update_hier=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_fed_toggle_routing_resources=1</TD>
   <TD>pacommandnames_goto_netlist_design=3</TD>
   <TD>pacommandnames_open_hardware_manager=5</TD>
   <TD>pacommandnames_program_fpga=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_run_bitgen=3</TD>
   <TD>pacommandnames_run_implementation=1</TD>
   <TD>pacommandnames_run_synthesis=9</TD>
   <TD>pacommandnames_set_as_top=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_show_connectivity=1</TD>
   <TD>pacommandnames_simulation_live_break=1</TD>
   <TD>pacommandnames_simulation_live_run=1</TD>
   <TD>pacommandnames_simulation_live_step=11</TD>
</TR><TR ALIGN='LEFT'>   <TD>pacommandnames_simulation_relaunch=2</TD>
   <TD>pacommandnames_simulation_run_behavioral=5</TD>
   <TD>pacommandnames_zoom_in=1</TD>
   <TD>paviews_code=24</TD>
</TR><TR ALIGN='LEFT'>   <TD>paviews_project_summary=13</TD>
   <TD>paviews_schematic=8</TD>
   <TD>paviews_timing_constraints=1</TD>
   <TD>programdebugtab_program_device=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>programfpgadialog_program=10</TD>
   <TD>progressdialog_background=1</TD>
   <TD>projectnamechooser_choose_project_location=1</TD>
   <TD>projectnamechooser_project_name=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>projecttab_close_design=1</TD>
   <TD>projecttab_reload=4</TD>
   <TD>rdicommands_delete=1</TD>
   <TD>rdicommands_properties=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>rdicommands_settings=2</TD>
   <TD>rdiviews_waveform_viewer=10</TD>
   <TD>removesourcesdialog_also_delete=1</TD>
   <TD>reporttimingsummarydialog_report_timing_summary_dialog_tabbed=3</TD>
</TR><TR ALIGN='LEFT'>   <TD>rungadget_show_error_and_critical_warning_messages=1</TD>
   <TD>rungadget_show_warning_and_error_messages_in_messages=1</TD>
   <TD>saveprojectutils_save=4</TD>
   <TD>schematicview_next=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>schmenuandmouse_expand_cone=3</TD>
   <TD>schmenuandmouse_report_timing_from_selected_object=1</TD>
   <TD>schmenuandmouse_select_all=1</TD>
   <TD>selectmenu_highlight=2</TD>
</TR><TR ALIGN='LEFT'>   <TD>selectmenu_mark=2</TD>
   <TD>settingsdialog_options_tree=1</TD>
   <TD>settingsdialog_project_tree=4</TD>
   <TD>settingseditorpage_use_this_drop_down_list_box_to_select=4</TD>
</TR><TR ALIGN='LEFT'>   <TD>signaltablepanel_signal_table=8</TD>
   <TD>simulationliverunforcomp_specify_time_and_units=2</TD>
   <TD>srcchooserpanel_add_or_create_source_file=12</TD>
   <TD>srcchooserpanel_create_file=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>srcchoosertable_src_chooser_table=3</TD>
   <TD>srcmenu_ip_hierarchy=13</TD>
   <TD>taskbanner_close=21</TD>
   <TD>touchpointsurveydialog_no=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>waveformview_goto_last_time=3</TD>
   <TD>xdccategorytree_xdc_category_tree=10</TD>
   <TD>xpowersettingsdialog_cancel=1</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>java_command_handlers</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>addsources=10</TD>
   <TD>autoconnecttarget=9</TD>
   <TD>editdelete=1</TD>
   <TD>editproperties=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>editundo=1</TD>
   <TD>fedtoggleroutingresourcescmdhandler=1</TD>
   <TD>launchprogramfpga=11</TD>
   <TD>newhardwaredashboard=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>newproject=1</TD>
   <TD>openhardwaremanager=9</TD>
   <TD>reportclocknetworks=1</TD>
   <TD>reporttiming=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>reporttimingsummary=1</TD>
   <TD>runbitgen=15</TD>
   <TD>runimplementation=4</TD>
   <TD>runschematic=20</TD>
</TR><TR ALIGN='LEFT'>   <TD>runsynthesis=24</TD>
   <TD>savefileproxyhandler=3</TD>
   <TD>settopnode=3</TD>
   <TD>showconnectivity=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>showpowerestimation=1</TD>
   <TD>showsource=1</TD>
   <TD>showview=9</TD>
   <TD>simulationbreak=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>simulationrelaunch=2</TD>
   <TD>simulationrun=4</TD>
   <TD>simulationrunfortime=1</TD>
   <TD>simulationstep=10</TD>
</TR><TR ALIGN='LEFT'>   <TD>timingconstraintswizard=1</TD>
   <TD>toolssettings=3</TD>
   <TD>viewtasksynthesis=18</TD>
   <TD>xdccreateclock=1</TD>
</TR><TR ALIGN='LEFT'>   <TD>zoomin=4</TD>
</TR>  </TABLE>
</TR><TR ALIGN='LEFT'>  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>other_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>guimode=5</TD>
</TR>  </TABLE>
  <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
   <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>project_data</B></TD></TR>
<TR ALIGN='LEFT'>   <TD>constraintsetcount=1</TD>
   <TD>core_container=false</TD>
   <TD>currentimplrun=impl_1</TD>
   <TD>currentsynthesisrun=synth_1</TD>
</TR><TR ALIGN='LEFT'>   <TD>default_library=xil_defaultlib</TD>
   <TD>designmode=RTL</TD>
   <TD>export_simulation_activehdl=0</TD>
   <TD>export_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_modelsim=0</TD>
   <TD>export_simulation_questa=0</TD>
   <TD>export_simulation_riviera=0</TD>
   <TD>export_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>export_simulation_xsim=0</TD>
   <TD>implstrategy=Vivado Implementation Defaults</TD>
   <TD>launch_simulation_activehdl=0</TD>
   <TD>launch_simulation_ies=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_modelsim=0</TD>
   <TD>launch_simulation_questa=0</TD>
   <TD>launch_simulation_riviera=0</TD>
   <TD>launch_simulation_vcs=0</TD>
</TR><TR ALIGN='LEFT'>   <TD>launch_simulation_xsim=8</TD>
   <TD>simulator_language=Mixed</TD>
   <TD>srcsetcount=7</TD>
   <TD>synthesisstrategy=Vivado Synthesis Defaults</TD>
</TR><TR ALIGN='LEFT'>   <TD>target_language=Verilog</TD>
   <TD>target_simulator=XSim</TD>
   <TD>totalimplruns=1</TD>
   <TD>totalsynthesisruns=1</TD>
</TR>  </TABLE>
</TR> </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>unisim_transformation</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>post_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=1</TD>
    <TD>carry4=17</TD>
    <TD>fdce=6</TD>
    <TD>fdpe=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=84</TD>
    <TD>fdse=2</TD>
    <TD>gnd=6</TD>
    <TD>ibuf=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1=4</TD>
    <TD>lut2=47</TD>
    <TD>lut3=4</TD>
    <TD>lut4=23</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5=6</TD>
    <TD>lut6=38</TD>
    <TD>obuf=24</TD>
    <TD>vcc=6</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>pre_unisim_transformation</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg=1</TD>
    <TD>carry4=17</TD>
    <TD>fdce=6</TD>
    <TD>fdpe=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre=84</TD>
    <TD>fdse=2</TD>
    <TD>gnd=6</TD>
    <TD>ibuf=10</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut1=4</TD>
    <TD>lut2=47</TD>
    <TD>lut3=4</TD>
    <TD>lut4=23</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut5=6</TD>
    <TD>lut6=38</TD>
    <TD>obuf=24</TD>
    <TD>vcc=6</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_drc</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-append=default::[not_specified]</TD>
    <TD>-checks=default::[not_specified]</TD>
    <TD>-fail_on=default::[not_specified]</TD>
    <TD>-force=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-format=default::[not_specified]</TD>
    <TD>-internal=default::[not_specified]</TD>
    <TD>-internal_only=default::[not_specified]</TD>
    <TD>-messages=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-name=default::[not_specified]</TD>
    <TD>-no_waivers=default::[not_specified]</TD>
    <TD>-return_string=default::[not_specified]</TD>
    <TD>-ruledecks=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-upgrade_cw=default::[not_specified]</TD>
    <TD>-waived=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>results</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>cfgbvs-1=1</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>report_utilization</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>clocking</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufgctrl_available=32</TD>
    <TD>bufgctrl_fixed=0</TD>
    <TD>bufgctrl_used=1</TD>
    <TD>bufgctrl_util_percentage=3.13</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufhce_available=72</TD>
    <TD>bufhce_fixed=0</TD>
    <TD>bufhce_used=0</TD>
    <TD>bufhce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufio_available=20</TD>
    <TD>bufio_fixed=0</TD>
    <TD>bufio_used=0</TD>
    <TD>bufio_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufmrce_available=10</TD>
    <TD>bufmrce_fixed=0</TD>
    <TD>bufmrce_used=0</TD>
    <TD>bufmrce_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>bufr_available=20</TD>
    <TD>bufr_fixed=0</TD>
    <TD>bufr_used=0</TD>
    <TD>bufr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>mmcme2_adv_available=5</TD>
    <TD>mmcme2_adv_fixed=0</TD>
    <TD>mmcme2_adv_used=0</TD>
    <TD>mmcme2_adv_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>plle2_adv_available=5</TD>
    <TD>plle2_adv_fixed=0</TD>
    <TD>plle2_adv_used=0</TD>
    <TD>plle2_adv_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>dsp</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>dsps_available=90</TD>
    <TD>dsps_fixed=0</TD>
    <TD>dsps_used=0</TD>
    <TD>dsps_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>io_standard</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>blvds_25=0</TD>
    <TD>diff_hstl_i=0</TD>
    <TD>diff_hstl_i_18=0</TD>
    <TD>diff_hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_hstl_ii_18=0</TD>
    <TD>diff_hsul_12=0</TD>
    <TD>diff_mobile_ddr=0</TD>
    <TD>diff_sstl135=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl135_r=0</TD>
    <TD>diff_sstl15=0</TD>
    <TD>diff_sstl15_r=0</TD>
    <TD>diff_sstl18_i=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>diff_sstl18_ii=0</TD>
    <TD>hstl_i=0</TD>
    <TD>hstl_i_18=0</TD>
    <TD>hstl_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>hstl_ii_18=0</TD>
    <TD>hsul_12=0</TD>
    <TD>lvcmos12=0</TD>
    <TD>lvcmos15=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvcmos18=0</TD>
    <TD>lvcmos25=0</TD>
    <TD>lvcmos33=1</TD>
    <TD>lvds_25=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lvttl=0</TD>
    <TD>mini_lvds_25=0</TD>
    <TD>mobile_ddr=0</TD>
    <TD>pci33_3=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>ppds_25=0</TD>
    <TD>rsds_25=0</TD>
    <TD>sstl135=0</TD>
    <TD>sstl135_r=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>sstl15=0</TD>
    <TD>sstl15_r=0</TD>
    <TD>sstl18_i=0</TD>
    <TD>sstl18_ii=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>tmds_33=0</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>memory</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>block_ram_tile_available=50</TD>
    <TD>block_ram_tile_fixed=0</TD>
    <TD>block_ram_tile_used=0</TD>
    <TD>block_ram_tile_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb18_available=100</TD>
    <TD>ramb18_fixed=0</TD>
    <TD>ramb18_used=0</TD>
    <TD>ramb18_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>ramb36_fifo_available=50</TD>
    <TD>ramb36_fifo_fixed=0</TD>
    <TD>ramb36_fifo_used=0</TD>
    <TD>ramb36_fifo_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>primitives</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bufg_functional_category=Clock</TD>
    <TD>bufg_used=1</TD>
    <TD>carry4_functional_category=CarryLogic</TD>
    <TD>carry4_used=17</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdce_functional_category=Flop &amp; Latch</TD>
    <TD>fdce_used=6</TD>
    <TD>fdpe_functional_category=Flop &amp; Latch</TD>
    <TD>fdpe_used=3</TD>
</TR><TR ALIGN='LEFT'>    <TD>fdre_functional_category=Flop &amp; Latch</TD>
    <TD>fdre_used=84</TD>
    <TD>fdse_functional_category=Flop &amp; Latch</TD>
    <TD>fdse_used=2</TD>
</TR><TR ALIGN='LEFT'>    <TD>ibuf_functional_category=IO</TD>
    <TD>ibuf_used=10</TD>
    <TD>lut1_functional_category=LUT</TD>
    <TD>lut1_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut2_functional_category=LUT</TD>
    <TD>lut2_used=47</TD>
    <TD>lut3_functional_category=LUT</TD>
    <TD>lut3_used=4</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut4_functional_category=LUT</TD>
    <TD>lut4_used=23</TD>
    <TD>lut5_functional_category=LUT</TD>
    <TD>lut5_used=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut6_functional_category=LUT</TD>
    <TD>lut6_used=38</TD>
    <TD>obuf_functional_category=IO</TD>
    <TD>obuf_used=24</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>slice_logic</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>f7_muxes_available=16300</TD>
    <TD>f7_muxes_fixed=0</TD>
    <TD>f7_muxes_used=0</TD>
    <TD>f7_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>f8_muxes_available=8150</TD>
    <TD>f8_muxes_fixed=0</TD>
    <TD>f8_muxes_used=0</TD>
    <TD>f8_muxes_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_available=20800</TD>
    <TD>lut_as_logic_fixed=0</TD>
    <TD>lut_as_logic_used=109</TD>
    <TD>lut_as_logic_util_percentage=0.52</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_available=9600</TD>
    <TD>lut_as_memory_fixed=0</TD>
    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_flip_flop_available=41600</TD>
    <TD>register_as_flip_flop_fixed=0</TD>
    <TD>register_as_flip_flop_used=95</TD>
    <TD>register_as_flip_flop_util_percentage=0.23</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_as_latch_available=41600</TD>
    <TD>register_as_latch_fixed=0</TD>
    <TD>register_as_latch_used=0</TD>
    <TD>register_as_latch_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_luts_available=20800</TD>
    <TD>slice_luts_fixed=0</TD>
    <TD>slice_luts_used=109</TD>
    <TD>slice_luts_util_percentage=0.52</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_available=41600</TD>
    <TD>slice_registers_fixed=0</TD>
    <TD>slice_registers_used=95</TD>
    <TD>slice_registers_util_percentage=0.23</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_distributed_ram_fixed=0</TD>
    <TD>lut_as_distributed_ram_used=0</TD>
    <TD>lut_as_logic_available=20800</TD>
    <TD>lut_as_logic_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_logic_used=109</TD>
    <TD>lut_as_logic_util_percentage=0.52</TD>
    <TD>lut_as_memory_available=9600</TD>
    <TD>lut_as_memory_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_as_memory_used=0</TD>
    <TD>lut_as_memory_util_percentage=0.00</TD>
    <TD>lut_as_shift_register_fixed=0</TD>
    <TD>lut_as_shift_register_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>lut_in_front_of_the_register_is_unused_fixed=0</TD>
    <TD>lut_in_front_of_the_register_is_unused_used=3</TD>
    <TD>lut_in_front_of_the_register_is_used_fixed=3</TD>
    <TD>lut_in_front_of_the_register_is_used_used=6</TD>
</TR><TR ALIGN='LEFT'>    <TD>register_driven_from_outside_the_slice_fixed=6</TD>
    <TD>register_driven_from_outside_the_slice_used=9</TD>
    <TD>register_driven_from_within_the_slice_fixed=9</TD>
    <TD>register_driven_from_within_the_slice_used=86</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_available=8150</TD>
    <TD>slice_fixed=0</TD>
    <TD>slice_registers_available=41600</TD>
    <TD>slice_registers_fixed=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>slice_registers_used=95</TD>
    <TD>slice_registers_util_percentage=0.23</TD>
    <TD>slice_used=41</TD>
    <TD>slice_util_percentage=0.50</TD>
</TR><TR ALIGN='LEFT'>    <TD>slicel_fixed=0</TD>
    <TD>slicel_used=27</TD>
    <TD>slicem_fixed=0</TD>
    <TD>slicem_used=14</TD>
</TR><TR ALIGN='LEFT'>    <TD>unique_control_sets_available=8150</TD>
    <TD>unique_control_sets_fixed=8150</TD>
    <TD>unique_control_sets_used=10</TD>
    <TD>unique_control_sets_util_percentage=0.12</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o5_and_o6_fixed=0.12</TD>
    <TD>using_o5_and_o6_used=13</TD>
    <TD>using_o5_output_only_fixed=13</TD>
    <TD>using_o5_output_only_used=0</TD>
</TR><TR ALIGN='LEFT'>    <TD>using_o6_output_only_fixed=0</TD>
    <TD>using_o6_output_only_used=96</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>specific_feature</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>bscane2_available=4</TD>
    <TD>bscane2_fixed=0</TD>
    <TD>bscane2_used=0</TD>
    <TD>bscane2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>capturee2_available=1</TD>
    <TD>capturee2_fixed=0</TD>
    <TD>capturee2_used=0</TD>
    <TD>capturee2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>dna_port_available=1</TD>
    <TD>dna_port_fixed=0</TD>
    <TD>dna_port_used=0</TD>
    <TD>dna_port_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>efuse_usr_available=1</TD>
    <TD>efuse_usr_fixed=0</TD>
    <TD>efuse_usr_used=0</TD>
    <TD>efuse_usr_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>frame_ecce2_available=1</TD>
    <TD>frame_ecce2_fixed=0</TD>
    <TD>frame_ecce2_used=0</TD>
    <TD>frame_ecce2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>icape2_available=2</TD>
    <TD>icape2_fixed=0</TD>
    <TD>icape2_used=0</TD>
    <TD>icape2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>pcie_2_1_available=1</TD>
    <TD>pcie_2_1_fixed=0</TD>
    <TD>pcie_2_1_used=0</TD>
    <TD>pcie_2_1_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>startupe2_available=1</TD>
    <TD>startupe2_fixed=0</TD>
    <TD>startupe2_used=0</TD>
    <TD>startupe2_util_percentage=0.00</TD>
</TR><TR ALIGN='LEFT'>    <TD>xadc_available=1</TD>
    <TD>xadc_fixed=0</TD>
    <TD>xadc_used=0</TD>
    <TD>xadc_util_percentage=0.00</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>synthesis</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-assert=default::[not_specified]</TD>
    <TD>-bufg=default::12</TD>
    <TD>-cascade_dsp=default::auto</TD>
    <TD>-constrset=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-control_set_opt_threshold=default::auto</TD>
    <TD>-directive=default::default</TD>
    <TD>-fanout_limit=default::10000</TD>
    <TD>-flatten_hierarchy=default::rebuilt</TD>
</TR><TR ALIGN='LEFT'>    <TD>-fsm_extraction=default::auto</TD>
    <TD>-gated_clock_conversion=default::off</TD>
    <TD>-generic=default::[not_specified]</TD>
    <TD>-include_dirs=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-keep_equivalent_registers=default::[not_specified]</TD>
    <TD>-max_bram=default::-1</TD>
    <TD>-max_bram_cascade_height=default::-1</TD>
    <TD>-max_dsp=default::-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-max_uram=default::-1</TD>
    <TD>-max_uram_cascade_height=default::-1</TD>
    <TD>-mode=default::default</TD>
    <TD>-name=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-no_lc=default::[not_specified]</TD>
    <TD>-no_srlextract=default::[not_specified]</TD>
    <TD>-no_timing_driven=default::[not_specified]</TD>
    <TD>-part=xc7a35tcsg324-1</TD>
</TR><TR ALIGN='LEFT'>    <TD>-resource_sharing=default::auto</TD>
    <TD>-retiming=default::[not_specified]</TD>
    <TD>-rtl=default::[not_specified]</TD>
    <TD>-rtl_skip_constraints=default::[not_specified]</TD>
</TR><TR ALIGN='LEFT'>    <TD>-rtl_skip_ip=default::[not_specified]</TD>
    <TD>-seu_protect=default::none</TD>
    <TD>-sfcu=default::[not_specified]</TD>
    <TD>-shreg_min_size=default::3</TD>
</TR><TR ALIGN='LEFT'>    <TD>-top=hexseg8</TD>
    <TD>-verilog_define=default::[not_specified]</TD>
</TR>   </TABLE>
   </TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>usage</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>elapsed=00:00:17s</TD>
    <TD>hls_ip=0</TD>
    <TD>memory_gain=509.621MB</TD>
    <TD>memory_peak=761.059MB</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
 <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
  <TR ALIGN='CENTER' BGCOLOR='#A7BFDE'><TD COLSPAN='1'><B>xsim</B></TD></TR>
   <TR><TD>
   <TABLE BORDER='1' CELLSPACING='0' WIDTH='100%'>
    <TR ALIGN='CENTER' BGCOLOR='#DBE5F1'><TD COLSPAN='4'><B>command_line_options</B></TD></TR>
<TR ALIGN='LEFT'>    <TD>-sim_mode=behavioral</TD>
    <TD>-sim_type=default::</TD>
</TR>   </TABLE>
   </TD></TR>
  </TABLE><BR>
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